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    • 专利摘要:
    PURPOSE: A driver for a liquid crystal display panel is to reduce power consumption, a circuit area, and a picture flickering. CONSTITUTION: The liquid crystal display panel includes a driver having a pair of first and second digital-to-analog(D/A) converters, a pair of corresponding first and second polarity switches, and a plurality of switching devices. The first D/A converter receives a picture signal and outputs a positive polarity voltage while the second D/A converter receives a picture signal and outputs a negative polarity voltage. The first polarity switch is connected to the outputs of the first and second D/A converters and alternately outputs the negative polarity voltage and the positive polarity voltage. The second polarity switch is also connected to the outputs of the first and second D/A converters and outputs a reverse polarity voltage. The switching devices are connected between the output of the first D/A converter and the first polarity switch and between the output of the second D/A converter and the second polarity switch. The switching devices are operated until output voltages of the first and second D/A converters are almost equal to each other.
    公开号:KR20000004893A
    申请号:KR1019980062701
    申请日:1998-12-31
    公开日:2000-01-25
    发明作者:신야 우도；세이지 야마가따；마사또시 고꾸분
    申请人:아끼구사 나오유끼；후지쯔 가부시끼가이샤；
    IPC主号:
    专利说明:

    Driver for liquid crystal display panel
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to liquid crystal display panels, and more particularly to drivers for liquid crystal display panels that reduce circuit area and power consumption and improve the image quality of liquid crystal display panels.
    In order to extend the life of the liquid crystal display panel, the driver reversed the polarity of the image voltage supplied to each pixel cell of the liquid crystal display panel (LCD panel).
    1 is a partial block circuit diagram of a conventional data driver 11 for a liquid crystal display panel. The data driver 11 includes a plurality of pairs of first and second digital-to-analog (D / A) converters 12 and 13, a plurality of sets of output terminals P1, P2, P3, and P4, and a plurality of pairs of polarity switching switches ( 16,17), shift registers and latch circuits (both not shown). The latch circuit latches the digital image signal supplied from the external device in accordance with the latch control pulse signal from the shift register.
    The pair of polarity switching switches 16 and 17 are connected between the first and second D / A converters 12 and 13 and the pair of output terminals, respectively. The polarity switching switch 16 selectively connects the output terminal of the first or second D / A converter 12 or 13 and the odd output terminals P1, P3. The polarity switching switch 17 selectively connects the output terminal of the first or second D / A converter 12 or 13 and the even output terminals P2 and P4. Each of the polarity switching switches 16 and 17 includes first and second switches 18 and 19.
    Each of the first and second D / A converters 12, 13 includes a selector 14 and an operational amplifier 15. The selector 14 of the first D / A converter 12 receives an image signal from the latch circuit as the first image signal Vd1 (Vd3) and receives first gray voltages Va1 to Va64. The selector 14 selects one of the first gray voltages Va1 to Va64 according to the first image signal Vd1 (Vd3) and outputs the selected signal to the operational amplifier 15. The operational amplifier 15 outputs the selected signal as a segment voltage. In this way, the first D / A converter 12 receives the first image signal Vd1 (Vd3) and the first gray voltages Va1 to Va64 and outputs a segment voltage (positive voltage) higher than the common voltage.
    The selector 14 of the second D / A converter 13 receives an image signal from the latch circuit as the second image signal Vd2 (Vd4) and receives second gray voltages Vb1 to Vb64. The selector 14 selects one of the second gray voltages Vb1 to Vb64 according to the second image signal Vd2 (Vd4) and outputs the selected signal to the operational amplifier 15. The operational amplifier 15 outputs the signal selected as the segment voltage. In this way, the second D / A converter 13 receives the second image signal Vd2 (Vd4) and the second gray voltages Vb1 to Vb64 and outputs a segment voltage (cathode voltage) lower than the common voltage.
    The first switch 18 of the polarity changeover switch 16 is connected between the first D / A converter 12 and the odd numbered output terminal P1 (P3). The first switch 18 of the polarity changeover switch 17 is connected between the output terminal of the second D / A converter 13 and the even output terminal P2 (P4).
    The second switch 19 of the polarity changeover switch 16 is connected between the output terminal of the first D / A converter 12 and the even output terminal P2 (P4). The second switch 19 of the polarity changeover switch 17 is connected between the output terminal of the second D / A converter 13 and the odd output terminal P1 (P3).
    The first and second switches 18, 19 turn on and off complementarily every 1 horizontal syringe in response to the polarity switching signal FR. Therefore, the positive and negative segment voltages are alternately supplied to each of the output terminals P1 to P4 every one horizontal syringe.
    For example, when the first switch 18 is turned on and the second switch 19 is turned off in response to the polarity switching signal FR, the bipolar segment voltage from the first D / A converter 12 has an odd number of output terminals ( P1 (P3) and a negative segment voltage from the second D / A converter 13 to an even output terminal P2 (P4).
    Then, when the first switch 18 is turned off and the second switch 19 is turned on in the horizontal period, the bipolar segment voltage from the first D / A converter 12 is applied to an even number of output terminals P2 (P4). The negative segment voltage is also applied from the second D / A converter 13 to the odd output terminals P1 (P3).
    The segment voltage applied to each output terminal is supplied to the pixel cell of the liquid crystal display panel through the data line. The display level (luminance) of the pixel cell varies depending on the potential difference between the common voltage and the segment voltage VS. Since the pixel cell includes a liquid crystal cell and an auxiliary storage capacitor, the liquid crystal display panel has a capacitive load on the data driver. Therefore, the first D / A converter 12 charges the pixel cell through the data line, and the second D / A converter 13 discharges the charge accumulated from the pixel cell through the data line. In this charge / discharge operation, the power consumption of the liquid crystal display panel increases as the number of horizontal pixel cells increases.
    2 is a partial block diagram of an improved data driver 21 to prevent an increase in power consumption. The data driver 21 includes a D / A converter 22 corresponding to the number of output terminals. Each of the D / A converters includes a selector 23 and an operational amplifier 24, and receives an image signal Vd and gray voltages V1 to V128, and also has a positive segment voltage Vs1 and a negative segment voltage Vs2. ) Is printed alternately. The gray voltages V65 to V128 are bipolar segment voltages higher than the common voltage applied to each pixel cell, and the gray voltages V1 to V64 are bipolar segment voltages lower than the common voltage. Therefore, each of the D / A converters 13 alternately outputs one of the gray voltages V65 to V128 and one of the gray voltages V1 to V64 as the segment voltage Vs. The polarities of the gradation voltages selected by the adjacent D / A converters 13 during the same horizontal syringes are different from each other.
    For example, as shown in FIG. 3A, the first D / A converter 22 alternately outputs the positive segment voltage Vsa and the negative segment voltage Vsb every one horizontal syringe. The second D / A converter 23 adjacent to the first D / A converter 22 alternately outputs the negative segment voltage Vsb and the positive segment voltage Vsa for each horizontal syringe as shown in FIG. 3B. do.
    Each switch 25 is connected between adjacent odd-numbered output terminals P1 (P3) and even-numbered output terminals P2, P4. Each switch 25 is turned on in response to the control signal ER for a predetermined period (e.g., a regression period, which is a non-selection period of the pixel cell) so that the data line is discharged to the cathode voltage from the data line in which the charge is charged to the anode voltage. To move through the switches 25. In this case, the D / A converter 22 is kept in a high impedance state. This charge / discharge causes the voltage of the data line connected to the output terminals P1 to P4 to be close to the common voltage. The D / A converter is charged / discharged to vary from the common voltage to the desired voltage. Since the charge / discharge operation of these converters 22 is performed around the common voltage, power consumption is reduced.
    However, since the data driver 21 of FIG. 2 requires a signal generator circuit for generating the control signal ER of the switch 25, the circuit area of the data driver 21 increases. The D / A converters 22 output positive / negative segment voltages so that they have almost the same circuit area as the first and second D / A converters 12 and 13 in FIG. For this reason, it is difficult to increase the number of display pixels within a limited area.
    4 is a schematic block diagram of another conventional data driver 111. The data driver 111 includes a digital unit 112 and a digital-to-analog (D / A) converter 22. The digital unit 112 includes a latch circuit 114 and a shift register (not shown).
    The shift register sequentially transmits a latch control pulse signal, and supplies this latch control pulse to each of the latch circuits 114.
    The latch circuit 114 corresponds to the D / A converter 22. 4 shows only one of the latch circuits 114. Each latch circuit 114 latches the image signal DD in accordance with the latch control pulse signal from the shift register, and supplies this latched signal to the corresponding D / A converter 22 as the image signal Vd. .
    Each D / A converter 22 is connected to an external output terminal P. Therefore, when the number of pixels of the liquid crystal display panel increases, the number of D / A converters 22 increases, and the circuit area of the data driver 111 increases.
    5 is a schematic block diagram of another conventional data driver 210. The data driver 210 includes first to fourth digital-to-analog (D / A) converters 211 to 214, input switching circuits 215a and 215b, output switching circuits 216a and 216b, shift registers and latch circuits ( Not shown). Adjacent first and second D / A converters 211 and 212 and adjacent third and fourth D / A converters 213 and 214 respectively form a pair.
    The input switching circuit 215a receives n-bit image signals D1n and D2n from the latch circuit. Then, in response to the polarity switching signal S1, the circuit 215a sends one of the image signals D1n and D2n to the first D / A converter 211 and an image signal to the second D / A converter 212. The other one of (D1n, D2n) is selectively output.
    The input switching circuit 215b receives n-bit image signals D3n and D4n from the latch circuit. In response to the polarity switching signal S1, the circuit 215b draws one of the image signals D3n and D4n to the third D / A converter 213 and the image signal (to the second D / A converter 214). Selectively outputs the other of D3n and D4n).
    The first D / A converter 211 selects the gray scale voltage according to the image signal from the input switching circuit 215a and outputs the bipolar segment voltage Vs1 higher than the common voltage to the output switching circuit 216a.
    The second D / A converter 212 selects the gray scale voltage according to the image signal from the input switching circuit 215a and outputs the negative segment voltage Vs2 lower than the common voltage to the output switching circuit 216a.
    The third D / A converter 213 selects the gray scale voltage according to the image signal from the input switching circuit 215b and outputs the bipolar segment voltage Vs3 higher than the common voltage to the output switching circuit 216b.
    The fourth D / A converter 214 selects the gray scale voltage according to the image signal from the input switching circuit 215b and outputs the negative segment voltage Vs4 lower than the common voltage to the output switching circuit 216b.
    The output switching circuit 216a outputs the positive voltage Vs1 from the first D / A converter 211 and the negative voltage Vs2 from the second D / A converter 212 according to the polarity switching signal S1. Are selectively output to the fields P1 and P2.
    The output switching circuit 216b selectively outputs the bipolar voltage Vs3 from the third D / A converter 213 to the output terminals P3 and P4 in accordance with the polarity switching signal S1.
    6 is a circuit diagram of the output switching circuit 216a. The output switching circuit 216a includes four CMOS transfer gates 217a to 217d and an inverter circuit 218.
    The output terminal of the first D / A converter 211 is connected to the output terminals P1 and P2 via the transmission gates 217a and 217c. The output terminal of the second D / A converter 212 is connected to the output terminals P1 and P2 through the transmission gates 217b and 217d.
    The NMOS transistor gates of the transfer gates 217a and 217d and the PMOS transistor gates of the transfer gates 217b and 217c receive the polarity switching signal S1. The PMOS transistor gates of the transfer gates 217a and 217d and the NMOS transistor gates of the transfer gates 217b and 217c receive the polarity switching signal S1 inverted by the inverter circuit 218. Since the output switching circuit 216b has the same configuration as the output switching circuit 216a, its detailed description is omitted. The input switching circuits 215a and 215b also have the same configuration as the output switching circuit 216a.
    For example, as shown in FIG. 7, the input switching circuit 215a supplies the image signal D1n to the first D / A converter 211 in response to the polarity switching signal S1 having the H (high) level. The image signal D2n is supplied to the second D / A converter 212. The transfer gates 217a and 217d of the output switching circuit 216a are electrically connected in response to the polarity switching signal S1 having the H level, and the transfer gates 217b and 217c are not electrically connected. In this way, the positive voltage Vs1 is supplied to the output terminal P1 through the transfer gate 217a, and the negative voltage Vs2 is supplied to the output terminal P2 through the transfer gate 217d. The level of the polarity switching signal S1 is switched every one horizontal syringe.
    8, the input switching circuit 215a supplies the image signal D1n to the second D / A converter 212 in response to the polarity switching signal S1 having the L (low) level. The image signal D2n is supplied to the first D / A converter 211. The input switching circuit 215b also operates in the same manner as the input switching circuit 215a. The transfer gates 217b and 217c of the output switching circuit 216a are electrically connected in response to the polarity switching signal S1 having the H level, and the transfer gates 217a and 217d are not electrically connected. In this way, the positive voltage Vs1 is supplied to the output terminal P2 through the transfer gate 217c, and the negative voltage Vs2 is supplied to the output terminal P1 through the transfer gate 217b.
    As described above, the data driver 210 inverts the polarity of the image voltage supplied to each pixel cell of the liquid crystal display panel so as to extend the life of each pixel cell. However, if the inversion operation of each pixel cell is delayed, flicker may occur in an image displayed on the liquid crystal display panel. In particular, when the polarities of all the pixel cells are inverted, the luminance unevenness of all adjacent pixel cells increases, thereby increasing image flicker.
    An object of the present invention is to provide a driver for a liquid crystal display panel with low power consumption.
    It is a second object of the present invention to provide a driver for a liquid crystal display panel having a reduced circuit area.
    A third object of the present invention is to provide a driver for a liquid crystal display panel with reduced image flickering.
    1 is a partial block circuit diagram of a conventional data driver for a first liquid crystal display panel.
    2 is a partial block diagram of a conventional second data driver.
    3A and 3B are waveform diagrams of the voltage output of the D / A converter of the data driver of FIG.
    4 is a schematic block diagram of a conventional third data driver.
    5 is a schematic block diagram of a conventional fourth data driver.
    6 is a circuit diagram of an output switching circuit of the data driver of FIG.
    7 and 8 illustrate the operation of the data driver of FIG.
    9 is a block circuit diagram of a liquid crystal display device.
    Fig. 10 is a block circuit diagram of a data driver according to a first embodiment of the present invention.
    FIG. 11 is a block diagram of a first modification of the data driver of FIG. 10.
    12 is a waveform diagram of a voltage output of the data driver of FIG.
    Fig. 13 is a block diagram of a data driver of a second modification.
    14 is a block diagram of a third modification of the data driver of FIG. 10;
    FIG. 15 is a block diagram of a fourth modification of the data driver of FIG. 10.
    16 is a block diagram of a fifth modification of the data driver of FIG. 10.
    FIG. 17 is a block diagram of a sixth modification of the data driver of FIG. 10.
    18 is a block diagram of a seventh modification of the data driver of FIG. 10;
    Figure 19 is a general block diagram of a driver of the present invention.
    20 is a block diagram of a data driver and a liquid crystal display panel according to a second embodiment of the present invention.
    21 is a schematic block circuit diagram of one of the data driver IC chips of FIG. 20;
    22 is a schematic block diagram of the IC chip of FIG. 21 having a time division drive control circuit.
    Fig. 23 is a detailed block diagram of the time division drive control circuit.
    24A is a waveform diagram of a time division control signal.
    24B is a waveform diagram of a voltage output of the D / A converter of the IC chip of FIG. 21;
    Fig. 25 is a schematic block circuit diagram of a first example of a data driver according to the third embodiment of the present invention.
    Fig. 26 is a block diagram of a second example of the data driver of the third embodiment.
    27 is a block diagram of a data driver according to a fourth embodiment of the present invention.
    FIG. 28 is a block diagram of an output switching circuit of the data driver of FIG. 27. FIG.
    29 and 30 are diagrams illustrating voltage inversion operations of one pixel unit of the data driver of FIG. 27;
    31 and 32 are diagrams illustrating voltage inversion operations of two pixel units of the data driver of FIG. 27;
    33 is a block diagram of a data driver according to a fifth embodiment of the present invention.
    34 is a block diagram of a data driver according to a sixth embodiment of the present invention.
    35 is a block diagram of a data driver according to a seventh embodiment of the present invention.
    36 is a block diagram of a data driver according to an eighth embodiment of the present invention.
    37 is a block diagram of an eighth modification of the data driver of FIG. 10;
    Briefly, the present invention provides a driver for a display panel including a plurality of pairs of first and second D / A converters, a plurality of pairs of first and second polarity switching switches, and a plurality of switching elements. Each of the first and second D / A converters has an output terminal. Each first D / A converter receives an image signal and outputs a positive voltage, and each second D / A converter receives an image signal and outputs a negative voltage. Each first polarity switching switch is connected to the output terminals of the first and second D / A converters and alternately outputs the positive voltage and the negative voltage in response to the polarity switching signal. Each second polarity switching switch is connected to the output terminals of the first and second D / A converters, and alternately outputs a reverse polarity voltage as opposed to the first polarity switching switch in response to the polarity switching signal. Each of the plurality of switching elements is respectively between a first node located between the output terminal of the first D / A converter and the first polarity switching switch and between a second node located between the output terminal of the second D / A converter and the second polarity switching switch. Connected. Each switching element is operated until the voltages of the first and second nodes are approximately equal.
    The present invention provides a driver for a display panel including a plurality of pairs of first and second D / A converters and a plurality of pairs of first and second switching circuits. Each of the first and second D / A converters has an output terminal. Each first D / A converter receives an image signal and alternately outputs a positive voltage and a negative voltage. Each second D / A converter receives an image signal and alternately outputs a negative voltage and a positive voltage as opposed to the first D / A converter. Each of the first and second switching circuits is connected between the output terminals of the first and second D / A converters. Each of the first and second switching circuits is electrically connected so that the voltages at the output terminals of the first and second D / A converters are approximately equal to each other based on the output voltages at the output terminals of the first and second D / A converters. Become. Since each of the first and second switching circuits is connected and electrically connected between the output terminals of the first and second D / A converters, the voltage at the output terminals of the first and second D / A converters is equal to the second D / A converter. They are almost equal to each other based on the output voltage of.
    The present invention provides a liquid crystal display device comprising a plurality of pairs of first and second data lines and a driver connected to the plurality of pairs of first and second data lines. The driver includes a plurality of pairs of first and second D / A converters having output terminals, a plurality of pairs of first and second polarity switching switches, and a plurality of switching elements. Each first D / A converter receives an image signal and outputs a positive voltage, and each second D / A converter receives an image signal and outputs a negative voltage. Each first polarity switching switch is connected between the output terminals of the first and second D / A converters and the first data line, and alternately outputs the positive and negative voltages to the first data line in response to the polarity switching signal. do. Each second polarity switching switch is connected between the output terminals of the first and second D / A converters and the second data line, and in response to the polarity switching signal, the second polarity switching switch reverses the reverse voltage to the first polarity switching switch as opposed to the first polarity switching switch. Output alternately. Each of the plurality of switching elements is connected between a first node located between the output terminal of the first D / A converter and the first data line and a second node located between the output terminal of the second D / A converter and the second polarity switching switch. . Each switching element is operated until the voltages of the first and second nodes are approximately equal to each other.
    The present invention provides a driver for a display panel including a plurality of D / A converters for receiving an image signal and outputting a display voltage, a plurality of output terminal groups assigned to the plurality of D / A converters, and a plurality of time division switches. . Each switch is connected between the D / A converter and the output terminal group respectively. Each switch is operated by a time division control signal to time-divisionally supply a display voltage from the D / A converter to the group of output terminals.
    The present invention provides a system for supplying a timing signal to a plurality of display panel drivers including first and second drivers. Each driver includes a semiconductor integrated circuit. The system includes wiring for connecting the first and second drivers in series. The first driver includes a plurality of D / A converters for receiving an image signal and outputting a display voltage, a plurality of output terminal groups assigned to the plurality of D / A converters, and a plurality of time division switches. Each switch is connected between each D / A converter and each output terminal group, and time-divisionally supplies a display voltage from the D / A converter to each group of output terminals according to the time division control circuit. The first driver further includes a time division setting circuit that generates a timing signal in response to the latch control pulse signal, and supplies a timing signal to a control circuit that receives the wiring and the timing signal and generates the time division control signal. The second driver includes a plurality of D / A converters for receiving an image signal and outputting a display voltage, a plurality of output terminal groups assigned to the plurality of D / A converters, and a plurality of time division switches. Each switch is connected between each D / A converter and each output terminal group to time-divisionally supply a display voltage from the D / A converter to each output terminal group in accordance with a time division control signal. The second driver further includes a control circuit that receives the timing signal from the first driver through the wiring and generates a time division control signal.
    The present invention provides a display panel driver including a first plurality of D / A converters for receiving an image signal and outputting a bipolar display voltage and a second plurality of D / A converters for receiving an image signal and outputting a negative display voltage. To provide. The first plurality of pairs of intermediate terminals are assigned to the first plurality of D / A converters, and the second plurality of pairs of intermediate terminals are assigned to the second plurality of D / A converters. The driver further includes a first plurality of time division switches and a second plurality of time division switches. Each of the first plurality of time division switches is connected between each of the first plurality of D / A converters and each pair of intermediate terminals of the first plurality of pairs, the first plurality of middle pairs from the D / A converter according to the time division control signal. Supply time-division to each pair of terminals. Each second plurality of time-division switches are connected between each of the second plurality of D / A converters and each pair of intermediate terminals of the second plurality of pairs, the second plurality of intermediate pairs from the D / A converter in accordance with the time division control signal. Supply time-division to each pair of terminals. The driver includes a plurality of pairs of output terminals including first and second output terminal pairs assigned to the first and second plurality of pairs of polarity switching switches, a first plurality of pairs of polarity switching switches and a second plurality of pairs of polarity switching switches. It further includes. Each of the first plurality of pairs of polarity switching switches selectively connects the first plurality of pairs of intermediate terminals and the first and second plurality of pairs of output terminals in accordance with the polarity switching signal. Each second plurality of pairs of polarity switching switches selectively connect the second plurality of pairs of intermediate terminals and the first and second plurality of pairs of output terminals in accordance with a polarity switching signal.
    The present invention provides a liquid crystal display device comprising a liquid crystal display panel having a plurality of data line groups and a driver for driving the liquid crystal display panel. The driver includes a plurality of D / A converters for receiving an image signal and outputting a display voltage, a plurality of output terminal groups assigned to the plurality of D / A converters and connected to the plurality of data line groups, respectively, and a plurality of time division switches. . Each switch is connected between each D / A converter and an output terminal of each group, and also time-divisionally supplies a display voltage from the D / A converter to each output terminal in accordance with a time division control signal.
    The present invention provides a plurality of pairs of first and second D / A converters, a plurality of pairs of first and second input switching circuits, and a plurality of pairs of first and second corresponding to the plurality of pairs of first and second D / A converters. A driver for a display panel including two output terminals, a plurality of pairs of first and second output switching circuits, and a plurality of control circuits is provided. Each first D / A converter receives an image signal and outputs a positive voltage, and each second D / A converter receives an image signal and outputs a negative voltage. Each switching circuit is connected to each pair of first and second D / A converters respectively and also selectively supplies an image signal to the first and second D / A converters. Each switching circuit is connected between each pair of first and second D / A converters and each pair of first and second output terminals and also receives a positive and negative voltage from the first and second D / A converters. And selectively to the second output terminal. Each of the first input and first output switching circuits is provided with control circuits for controlling the plurality of first input and output switching circuits, respectively, so that in the first mode, the adjacent output terminals of adjacent pairs of output terminals have different polarities. The voltage is supplied, and in the second mode, a voltage having the same polarity is supplied to adjacent output terminals of the adjacent pair of output terminals.
    The present invention provides a liquid crystal display device comprising a liquid crystal display panel having a plurality of pairs of first and second data lines and a driver for driving the liquid crystal display panel. The driver is connected to a plurality of pairs of first and second D / A converters, a plurality of pairs of first and second input switching circuits, a plurality of pairs of first and second data lines, and a plurality of pairs of first and second D lines. Each first D / A converter comprising a plurality of pairs of first and second output terminals corresponding to a / A converter, a plurality of pairs of first and second output switching circuits, and a plurality of control circuits, receives an image signal and A positive voltage is output, and each second D / A converter receives an image signal and outputs a negative voltage. Each switching circuit is connected to each pair of first and second D / A converters respectively and also selectively supplies an image signal to the first and second D / A converters. Each output switching circuit is connected between each pair of first and second D / A converters and each pair of first and second output terminals and also provides for a positive and negative voltage from the first and second D / A converters. Optionally supply to the 1st and 2nd output terminals. Each of the first input and first output switching circuits is provided with control circuits for controlling the plurality of first input and output switching circuits, respectively, so that in the first mode, voltages having different polarities in adjacent output terminals of adjacent pairs of output terminals are provided. In the second mode, a voltage having the same polarity is supplied to adjacent output terminals of the adjacent pair of output terminals.
    The present invention provides a method of driving a display panel. First, a plurality of pairs of first and second D / A converters are provided. Each first D / A converter receives an image signal and outputs a positive voltage, and each second D / A converter receives an image signal and outputs a negative voltage. A plurality of pairs of first and second input switching circuits are then provided. Each switching circuit is connected to each pair of first and second D / A converters and also selectively supplies an image signal to the first and second D / A converters. A plurality of first and second output terminals are then provided corresponding to the plurality of pairs of first and second D / A converters. A plurality of pairs of first and second output switching circuits are then provided. Each switching circuit is between each pair of first and second D / A converters and each pair of first and second output terminals and also converts the positive and negative voltages from the first and second D / A converters to the first and second D / A converters. Supply to the second output terminal selectively. Each first input and output switching circuit is respectively controlled such that voltages having different polarities are supplied to adjacent output terminals of adjacent pairs of output terminals in the first mode. The first input and output switching circuits are respectively controlled such that a voltage having the same polarity is supplied to adjacent output terminals of the adjacent pair of output terminals in the second mode.
    Other features and advantages of the invention can be clearly understood from the following examples, which are described with reference to the accompanying drawings which illustrate the principles of the invention.
    EXAMPLE
    (First embodiment)
    Like numbers refer to like elements in the figures.
    9 is a block diagram of the liquid crystal display device 31. The liquid crystal display device 31 includes a liquid crystal display panel (LCD panel) 32, a vertical driver (gate driver) 33, and a horizontal driver (data driver) 34. The liquid crystal display panel 32 includes scanning lines (gate wirings) G1 to Gn and data lines (drain wirings) D1 to D2m (n and m are integers) that cross each other.
    The pixel cells 39 are connected to the intersections of the scan lines G1 to Gn and the data lines D1 to D2m. Each pixel cell 39 includes an auxiliary (memory) capacitor 39a and a liquid crystal cell 39b as signal storage elements. The thin film transistor (TFT) 35 is connected between the pixel cell 39 and the data lines D1 to D2m, and the gate of the TFT is connected to the scan lines G1 to Gn.
    Each liquid crystal cell 39b has a first electrode (display electrode) connected to the source of the corresponding TFT 35 and a second electrode (common electrode) receiving the common voltage Vcom. The auxiliary capacitor 39a is connected in parallel with the liquid crystal cell 39b.
    The gate driver 33 is connected to each scan line G1 to Gn, and applies a scan signal (gate signal) to the scan lines G1 to Gn in accordance with a control signal. The data driver 34 is connected to each data line, and applies a segment voltage to each data line D1 to D2m in accordance with a control signal and an image signal. The gate driver 33 and the data driver 34 perform horizontal and vertical scanning according to the control signal and display an image on the liquid crystal display panel 32.
    10 is a block diagram of data driver 34. The data driver 34 includes first and second digital-to-analog (D / A) converters 12 and 13, first and second polarity switching switches 16 and 17, and shift registers and latch circuits (not shown). Include. M pairs of first and second D / A converters 12 and 13 are provided corresponding to data lines D1 to D2m.
    The pair of first and second polarity switching switches 16 and 17 are connected to a pair of first and second D / A converters 12 and 13 and a pair of odd and even output terminals P1 and P3, ..., P2m-1; P2, P4, ..., P2m).
    Each of the first and second D / A converters 12, 13 includes a selector 14 and an operational amplifier 15. The selector 14 of each first D / A converter 12 selects one of the first gray voltages Va1 to Va64 supplied from the latch circuit in accordance with the first image signals Vd1, Vd3, ..., Vd2m. This selection voltage is output to the operational amplifier 15. The operational amplifier 15 receives the selection voltage and outputs a first segment voltage (positive voltage) of Vs1 higher than the common voltage.
    The selector 14 of each second D / A converter 13 selects one of the second grayscale voltages Vb1 to Vb64 supplied from the latch circuit in accordance with the second image signals Vd2, Vd4, ..., Vd2m. The selection voltage is output to the operational amplifier 15. The operational amplifier 15 receives this selection voltage and outputs a second segment voltage (negative voltage) of Vs2 lower than the common voltage.
    The first polarity switching switch 16 is the first switch 18 and the second D connected between the output terminal of the first D / A converter 12 and the odd output terminals P1, P3, ..., P2m-1. And a second switch 19 connected between the output terminal of the / A converter 13 and the odd output terminals P1, P3, ..., P2m-1. The second polarity switching switch 17 is the first switch 18 and the first D connected between the output terminal of the second D / A converter 13 and the even output terminals P2, P4, ..., P2m-1. And a second switch 19 connected between the output terminal of the / A converter 13 and the even output terminals P2, P4, ..., P2m-1.
    The first and second switches 18, 19 turn on and off complementarily every 1 horizontal syringe in response to the switching control signal FR. In this on and off operation, the positive and negative segment voltages are alternately applied to each of the output terminals P1 to P2m every one horizontal syringe.
    The switching element MOS transistor 36 includes a node N1 located between the first D / A converter 12 and the first polarity switching switch 16, the second D / A converter 13, and the second polarity switching switch ( 17 is connected like a diode between nodes N2 located between them. Transistor 36 is preferably an N-channel MOS transistor. Transistor 36 has a source connected to node N2, a drain connected to node N1, and a gate connected to the source of transistor 36 (that is, node N2).
    By connecting to this, the transistor 36 includes a rectifier element (diode element) having an anode connected to the output terminal of the second D / A converter 13 and a cathode connected to the output terminal of the first D / A converter 12. It functions as) Therefore, a diode may be used instead of the transistor 36. P-channel MOS transistors can also be used. In this case, the gate of the P-channel MOS transistor is connected to the output terminal of the first D / A converter 12.
    For example, when the first switch 18 is turned on and the second switch 19 is turned off, the first segment voltage Vs1 is applied to the odd numbered output terminals P1, P3, ..., P2m-1, and The two-segment voltage Vs2 is applied to even-numbered output terminals P2, P4, ..., P2m. As a result, the odd data lines D1, D3, ..., D2m-1 are charged with the first bipolar segment voltage Vs1, and the even data lines D2, D4, ..., D2m are the second negative segment voltage. Discharged at (Vs2).
    The first switch 18 is then turned off during the horizontal syringe and when the second switch 19 is on, the voltage of the odd data lines D1, D3, ..., D2m-1 (i.e., the first bipolar segment voltage) (Vs1) is applied to the gate of the transistor 36 to turn the transistor 36 on. Then, current flows from the odd output terminals P1, P3, ..., P2m-1 through the transistor 36 to the even output terminals P2, P4, ..., P2m. In other words, the electric charges discharged from the odd output terminals P1, P3, ..., P2m-1 are charged to the even output terminals P2, P4, ..., P2m. Transistor 36 is turned on until the two voltages at nodes N1 and N2 (ie, the voltages at the output terminals of first and second D / A converters 12 and 13) are approximately equal. In other words, the voltage of the data line connected to both output terminals P2, P4, ..., P2m; P1, P3, ..., P2m-1 is charged / discharged until it reaches around the common voltage.
    Subsequently, the gate voltage of the transistor 36 is lower than the drain voltage by the second segment voltage Vs2 output from the second D / A converter 13. As a result, the transistor 36 is turned off to block the flow of current from the node N1 to the node N2.
    Then, when the first and second polarity switching switches 16 and 17 are switched during the horizontal syringe, a bipolar segment voltage is applied to the gate of the transistor 36 from an even number of output terminals P2, P4, ..., P2m so that the transistor 36 is turned on. In this way, the electric charges discharged from the even numbered output terminals P2, P4, ..., P2m are charged to the odd numbered output terminals P1, P3, ..., P2m-1. Since the transistor 36 is turned on and off and charged / discharged to the vicinity of the common voltage as described above, the first and second D / A converters 12 and 13 are centered on the common voltage to the positive or negative voltage. It is charged / discharged. In this way, the amount of charge / discharge is reduced, thereby reducing power consumption.
    In addition, since a control signal generation circuit for turning on and off the switch 25 as shown in the conventional data driver 21 of FIG. 2 is not necessary, an increase in the circuit area can be avoided.
    The data driver 34 of the present invention may be modified as shown in the following seven embodiments.
    11 is a block diagram of a first modification of the data driver 41. Two N-channel MOS transistors 36 and 42 are connected in series between the output terminals of the first and second D / A converters 12 and 13. Specifically, the transistor 42 is connected between the transistor 36 and the node N2, and a predetermined voltage Vr1 is applied to the gate of the transistor 42. The transistor 42 is turned off when the voltage of the node N2 drops to the predetermined voltage Vr1. In this way, the voltage at the node N2 is discharged until the voltage reaches the predetermined voltage Vr1.
    The predetermined voltage Vr1 is preferably set to the minimum value of the first bipolar segment voltage Vs1 supplied to the output terminals P1 and P2. The minimum voltage is higher than the common voltage Vcom as shown in FIG. Therefore, the first D / A converter 12 reduces the charge amount corresponding to the voltage difference between the predetermined voltage Vr1 and the common voltage Vcom, and supplies only the remaining charge amount. As a result, the charging time to the desired bipolar segment voltage is shortened, which reduces power consumption.
    In addition, when the transistor 42 is turned off, the output terminal (node N2) of the second D / A converter 13 is set to the maximum value of the second negative segment voltage Vs2. This causes the second D / A converter 13 to reliably discharge the data line connected to the output terminal P2 with one of the second gray voltages Vb1 to Vb64.
    13 is a block diagram of a second modification of the data driver 43. The data driver 43 includes a wiring 44 to which a predetermined voltage Vr1 is applied, a first N-channel MOS transistor 45 connected to the node N1 and the wiring 44, and a wiring 44 to the node N2. ) And a second N-channel MOS transistor 46 connected to each other. The first N-channel MOS transistor operates in the same manner as the transistor 36. The second transistor 46 is turned off when the voltage of the node N2 drops to the predetermined voltage Vr1. In this way, the voltage of the node N2 discharges until it reaches the predetermined voltage Vr1. As a result, charging time to the desired bipolar segment voltage is shortened, reducing power consumption.
    The predetermined voltage Vr1 is equal to or less than the minimum value of the first bipolar segment voltage Vs1 when the first transistor 45 is turned off, and the second negative polarity segment voltage Vs2 when the second transistor 46 is turned off. It is preferable to set above the maximum value. This reliably charges the data lines connected to the output terminals P1 and P2 by the first and second D / A converters 12 and 13 to the first and second gray voltages Va1 to Va64 and Vb1 to Vb64. And discharge.
    14 is a block diagram of a third modification of the data driver 51. The data driver 51 has an N-channel MOS transistor 52 connected in series between the output terminals of the first and second D / A converters 12 and 13 (that is, the nodes N1 and N2). P-channel MOS transistor 53 is provided. The first voltage V1 is supplied to the gate of the N-channel MOS transistor 52, and the second voltage V2 is supplied to the gate of the P-channel MOS transistor 53. The N-channel MOS transistor 52 is turned off when the voltage of the node N1 rises to the first voltage V1. The P-channel MOS transistor 53 turns off when the voltage at the node N2 drops to the second voltage V2. In other words, charging / discharging is executed until one of the transistors 52 and 53 is first turned off. Therefore, the amount of charge / discharge can be adjusted by setting the first and second voltages V1 and V2. In addition, the first and second voltages V2 may be set to the same voltage.
    Preferably, the first voltage V1 is set to the minimum value of the first bipolar segment voltage Vs1, and the second voltage V2 is set to the maximum value of the second negative segment voltage Vs2. When the transistor 52 is turned off, the output terminal (node N1) of the first D / A converter 12 is charged to the first voltage V1. In this way, the first D / A converter 12 reliably charges the data line connected to the node N1 to one of the first gray voltages Va1 to Va64. When the transistor 53 is turned off, the output terminal (node N2) of the second D / A converter 13 is charged to the second voltage V2. In this way, the second D / A converter 13 reliably discharges the data line connected to the node N2 to one of the gradation voltages Vb1 to Vb64.
    15 is a block diagram of a fourth modification of the data driver 55 suitable for the color liquid crystal display device. The data driver 55 is connected to the first and second D / A converters 12 and 13 corresponding to a pair of output terminals (eg, P1 and P4) connected to pixels displaying the same color (eg, red). A diode 56 is connected between the output terminals. Diode 57 connects the green D / A converter, and diode 58 connects the blue D / A converter. Instead of a diode, the transistors of FIGS. 10, 11, 13, 14 and 37 may be used. Since the pixel cells of the same color display the same color tone, the diodes are connected as described above. In other words, the potential difference between the positive (or negative) segment voltage resulting from the common voltage Vcom and the red image signal Vd1R, and the negative (or positive) resulting from the common voltage Vcom and the red image signal Vd2R. The potential difference between the segment voltages of is almost the same. In this way, since the charge / discharge efficiency for the output terminals P1 and P2 of the same color is improved by the diode, power consumption is reduced.
    FIG. 16 is a block diagram of a fifth modification of the data driver 61 having the conventional D / A converter 22 of FIG. The D / A converter 22 alternately outputs the positive and negative segment voltages. The data driver 61 has first and second switching circuits 62 and 63. The first and second switching circuits 62 and 63 are the nodes N11 located between the odd numbered output terminals P1 and the D / A converter 22 and the even numbered output terminals P2 and the D / A converter 22. It is connected between the nodes N12 located in the middle.
    The first switching circuit 62 includes an N-channel MOS transistor 64a, a P-channel MOS transistor 65a and an N-channel MOS transistor 66a. The N-channel MOS transistor 64a is connected between the node N11 and the node N12. The P-channel MOS transistor 65a is connected between the gate of the first transistor 64a and the node N11 and has a gate that receives the polarity switching signal FR. The N-channel MOS transistor 66a is connected between the gate of the first transistor 64a and the low potential power supply, and has a gate that receives the polarity switching signal FR.
    The second switching circuit 63 includes an N-channel MOS transistor 64b, a P-channel MOS transistor 65b and an N-channel MOS transistor 66b. N-channel MOS transistor 64b is connected between node N11 and node N12. The P-channel MOS transistor 65b is connected between the gate of the first transistor 64b and the node N11 and has a gate that receives the reverse polarity switching signal VFR inverted by the inverter circuit 67. The third transistor 66b is connected between the gate of the first transistor 64b and the low potential power supply, and has a gate that receives the reverse polarity switching signal XFR.
    The first and second switching circuits 62, 63 operate in the same manner as the transistor 36 of FIG. In this way, the power consumption of the data driver 61 having the D / A converter 22 is also reduced.
    In FIG. 17, the first and second switching circuits 62 and 63 are connected to a wiring for supplying a predetermined voltage Vr1 to the node N11 and the node N12.
    FIG. 18 is a block diagram of a seventh modification of the data driver 81 of FIG. 7. The data driver 81 includes first and second switching circuits 82 and 83 connected to the node N11 and the node N12. The first switching circuit 82 includes N-channel MOS transistors 84 and 85. The N-channel MOS transistor 84 is connected between the node N11 and the node N12, the N-channel MOS transistor 85 is connected between the gate of the N-channel MOS transistor 84 and the node N11, It has a gate to receive the polarity switching signal FR.
    The second switching circuit 83 includes N-channel MOS transistors 84 and 86. N-channel MOS transistor 84 is shared by first and second switching circuits 82 and 83. The N-channel MOS transistor 86 is connected between the gate of the N-channel MOS transistor 84 and the node N12 and has a gate that receives the reverse polarity switching signal XFR inverted by the inverter circuit 67. .
    The first and second switching circuits 82, 83 operate in the same manner as the transistor 36 of FIG. In this way, the power consumption of the data driver 81 including the D / A converter 22 is also reduced. Since the first and second switching circuits 82 and 83 share the first transistor 84, the circuit area is reduced.
    Fig. 19 is a block diagram showing an outline of a driver of the present invention. The driver includes a plurality of external output terminals P, a D / A converter 301 and a time division switch 341 connected to the data line D of the display panel. The D / A converter 301 receives the image signal Vd and outputs the display voltage Vs. The time division switch 341 is connected between the D / A converter 301 and the plurality of external output terminals P, and the display voltage Vs is transferred from the D / A converter 301 according to the time division control signal J. Time-division output to the external output terminal (P).
    (2nd Example)
    As shown in FIG. 20, the data driver 334 connected to the liquid crystal display panel 32 includes a plurality (in this case, five) integrated circuit devices or IC chips 336a to 336e connected in series. The IC chip 336a inputs the image signal DD and the control signal S and outputs the control signal S to the IC chip 336b of the next stage in accordance with the clock signal contained in the control signal. The control signal also includes a latch control pulse signal. Each IC chip 336b, 336e operates in the same manner as the first stage IC chip 336a, and transmits a control signal S.
    21 is a schematic block circuit diagram of the IC chip 336a. Each of the other IC chips 336b to 336e has the same configuration as the IC chip 336a.
    The IC chip 336a includes a digital unit 337, a plurality of digital-to-analog (D / A) converters 313, a plurality of time division switches 341, and external output terminals (pads) Pa and Pb. The digital unit 337 includes a latch circuit 338, a shift register (not shown), a time division drive control circuit (FIGS. 22 and 23) 339, and a control circuit (FIG. 23) 340. A pair of latch circuits 338 are connected to each of the D / A converters 313. 21 shows only a pair of latch circuits 338. The shift register is used to transmit the latch circuit control pulse signal.
    The control circuit 340 generates a time division control signal J having a pulse width half of one horizontal syringe shown in FIG. 24A, and the time division control signal J is applied to the latch circuit 338 and the time division switch 341. To feed. In other words, the time division control signal J is a pulse signal which repeats rising and falling edges between one horizontal syringe. The time division control signal J may be supplied from an external device.
    The odd latch circuit 338 outputs the latched image signal Vd to the D / A converter 313 in response to the rising edge of the time division control signal J. FIG. The even latch circuit 338 outputs the latched image signal Vd to the D / A converter 313 in response to the falling edge of the time division control signal J. FIG.
    Each D / A converter 313 alternately selects one of the positive gradation voltages V65 to V128 or the negative gradation voltages V1 to V64 so that each time-division control signal J falls, this selection segment Output the voltage Vs. As shown in Fig. 24B, the D / A converter 313 inverts the polarity of the segment voltage Vs every half of the horizontal syringes.
    Referring again to FIG. 21, a time division switch 341 is connected between one output terminal of each D / A converter 313 and a pair of even and odd pads Pa and Pb.
    Each time division switch 341 connects an output terminal of one of the D / A converters 313 and an even number of pads Pa in response to the rising edge of the time division control signal J, and also controls the time division control signal J. In response to the falling edge, an output terminal of one of the D / A converters 313 and an even pad Pa are connected. In other words, the segment voltage Vs from the D / A converter 313 is supplied to the odd pads Pa during the periods K1 and K3 in which the time division control signal J has the H level, as shown in FIGS. 24A and 24B. do. During the periods K2 and K4 in which the time division control signal J has an L level, the segment voltage Vs is supplied to even pads Pb. In this way, the positive and negative segment voltages Vs are alternately applied to each odd pad Pa and each even pad Pb between the horizontal syringes. The potential difference V1 between the common voltage Vcom and the segment voltage Vs corresponds to the display level (luminance) of the pixel cell.
    As shown in FIG. 22, each time division drive control circuit 339 is connected to the internal wiring L of each IC chip 336a to 336e. Each internal wiring L is interconnected by an external wiring 342 located between each IC chip 336a, 336e.
    23 is a block diagram of the time division drive control circuit 339. The time division drive control circuit 339 includes a CMOS transfer gate 343 and three inverter circuits 344 to 346. The inverter circuit 344 has an input terminal for receiving the latch control pulse signal (starting pulse signal) ST transmitted from the shift register (redistributed) and an output terminal connected to the internal wiring L through the transmission gate 343. Has The control circuit 340 is connected to the output of the inverter circuit 345, and the input of the inverter circuit 345 is connected to the internal wiring L.
    The P-channel MOS transistor gate of the transfer gate is connected to the external terminal 347 of the IC chip 336c, and the N-channel MOS transistor gate of the transfer gate is connected to the external terminal 347 through the inverter circuit 346. . The external terminal 347 is connected to the high potential power supply Vcc through the high potential fuse 348 and to the low potential power supply Vss through the low potential fuse 349.
    When the high potential fuse 348 is melted in the IC chip 336c positioned at the center of the IC chips 336a to 336e, the low potential power supply voltage is supplied to the external terminal 347. In this way, the transfer gate 343 in the IC chip 336c maintains the conductive state. The time division drive control circuit 339 of the IC chip 336c outputs the timing signal T to the external wiring 342 in response to the latch control pulse signal ST from the shift register. The control circuit 340 receives the timing signal / T from the inverter circuit 345 and generates a time division control signal J in accordance with the timing signal / T.
    In this embodiment, the latch control pulse signal ST is sequentially transmitted by the shift registers of the IC chips 336a to 336e. When the latch control pulse signal ST reaches the input terminal of the shift register of the center IC chip 336c, half of one horizontal syringe passes. The transfer gate 343 maintains the conductive state such that the reference time division control signal J is generated by the control circuit 340 of the center IC chip 336c. However, if the IC chip located at the midpoint during one horizontal syringe is the IC chip 336b or the IC chip 336d, the transfer gate 343 inside the IC chip may be kept in a conductive state. The number of IC chips can also be changed to 4 or less or 6 or more. For example, if the number of IC chips is set to eight, the five-stage IC chip is located at the midpoint between one horizontal syringe. In this way, the transfer gate 343 of the fifth stage IC chip is maintained in a conductive state.
    In order to generate the time division control signal J, a counter may be used instead of the control circuit 340 of the center IC chip 343. As soon as the latch control pulse signal ST reaches the shift register of the IC chip 336c, the counter counts the number of clock pulses of the latch control panel signal ST. The counter outputs time division control signal J when the number of clock pulses reaches a predetermined count.
    When the low potential fuse is melted on the remaining IC chips 336a, 336b, 336d, and 336e, a high potential power voltage is supplied to the external terminal 347. In this way, the transfer gate 343 in the IC chips 336a, 336b, 336d, and 336e is kept in a conductive state. The time division driving control circuit 339 in the IC chips 336a, 336b, 336d, and 336e receives the timing signal T from the time division driving control circuit 339 of the center IC chip 336c via the external wiring 342. . The control circuit 340 receives the timing signal T through the inverter circuit 345 to generate the time division control signal J. In this way, the time division switch 341 of the IC chips 336a, 336b, 336d and 336e is synchronized with the time division switch 341 of the center reference IC chip 336c.
    The second embodiment has the following advantages.
    (1) Since the time division control signal J is supplied to the time division switch 341 and the output terminal of the D / A converter 313 and the pads Pa and Pb are selectively connected, the number of D / A converters is equal to the pad ( Half of the number of Pa, Pb). In this way, the circuit area of the data driver 334 (that is, the size of the IC chips 336a to 336e) is reduced. In other words, the number of pixels for a liquid crystal display panel can be increased by only slightly increasing the circuit area.
    (2) The IC chips 336a to 336e of the data driver 334 are provided with a circuit for generating the time division control signal J. In this way the external device does not need its own circuitry.
    (3) The time division control signal J is supplied to the data driver 334 every horizontal syringe interval, and is easily generated in accordance with the latch control pulse signal.
    (4) The center IC chip 336c generates a time division control signal J for matching timing when the latch control pulse signal arrives at the input terminal of the shift register. Therefore, a timing signal for synchronizing the time division control signals J of all the IC chips 336a to 336e is not necessary. As a result, the circuit configuration of the data driver 34 is simplified.
    (5) The remaining IC chips 336a, 336b, 336d, and 336e generate a time division control signal J in accordance with the timing signal T output from the center IC chip 336c. In this way, the timing of the time division control signal J of the IC chip 336c and the timing of the time division control signal J of the remaining chips are accurately synchronized.
    (6) The timing signal T is supplied from the central IC chip 336c to the adjacent IC chips 336b and 336d via the external wiring 342 and from the IC chips 336b and 336d via the external wiring 342. It is supplied to adjacent IC chips 336a and 336e. Since the IC chips 336a to 336e are arranged in a linear manner, the external wiring 342 is relatively short. In addition, the total length of the external wiring 342 is shorter than the common wiring extending from the IC chip 336a to the IC chip 336e.
    (7) The IC chip 336c generating the reference timing signal T has an open high potential fuse 348 and the remaining IC chip receiving the timing signal T has the open low potential fuse 349 open. Have In this manner, each of the IC chips 336a to 336e may include a time division setting circuit 339 having the same configuration. As a result, the development cost and manufacturing cost of the IC chips 336a to 336e are reduced. In addition, since the remaining IC chips do not generate the time division control signal J according to the latch control signal pulse signal, the time division setting circuit 339 of the remaining IC chips may be omitted.
    (Third Embodiment)
    25 is a schematic block diagram of the IC chip 336f of the data driver 334 according to the third embodiment of the present invention. The IC chip 336f includes a digital unit 350, a plurality of pairs of first and second D / A converters 313H and 313L, a plurality of pairs of time division switches 341a and 341b, and a plurality of pairs of first intermediate terminals Ma1. , Ma2, a plurality of pairs of second intermediate terminals Mb1 and Mb2, a plurality of polarity switching switches 352, and a plurality of first to fourth pads P1 to P4. The digital unit 350 includes a plurality of first to fourth latch circuits 351a to 351d, a shift register (not shown), a time division driving control circuit 339 (FIG. 23), and a control circuit 340 (FIG. 23). Include. The pair of first and second latch circuits 351a and 351b correspond to the first D / A converter 313H, and the pair of third and fourth latch circuits 351c and 351d correspond to the second D / A. Corresponds to transducer 313L. FIG. 25 shows only four first to fourth latch circuits 351a to 351d for one of the plurality of pairs of D / A converters 313H and 313L.
    The first to fourth latch circuits 351a to 351d latch the image signal DD in response to the latch control pulse signal supplied from the shift register.
    During the first horizontal syringe, the first latch circuit 351a supplies the first latched image signal Vd to the first D / A converter 313H, and the second latch circuit 351b supplies the second latched image. The signal Vd is supplied to the second D / A converter 313L. The third latch circuit 351c supplies the third latched image signal Vd to the third D / A converter 313H, and the fourth latch circuit 351d removes the fourth latched image signal Vd. Supply to 4 D / A converter 313L. The third and fourth D / A converters described above become a pair of first and second D / A converters 313H and 313L.
    Then, during the second horizontal syringe interval, the second latch circuit 351b supplies the second latched image signal Vd to the first D / A converter 313H, and the first latch circuit 351a receives the first latch. The supplied image signal Vd is supplied to the second D / A converter 313L. The fourth latch circuit 351d supplies the fourth latched image signal Vd to the third D / A converter 313H, and the third latch circuit 351c removes the third latched image signal Vd. Supply to 4 D / A converter 313L.
    Thus, during the first and second horizontal syringes, the first and third D / A converters 313H respectively receive the first latched image signal and the third latched image signal, and then the second latched image signal. The fourth latched image signal is sequentially received. The second and fourth D / A converters 313L receive the second latched image signal and the fourth latched image signal, respectively, and then sequentially receive the first latched image signal and the third latched image signal. .
    Each first D / A converter 313H (that is, the first and third converters) selects one of the positive gray voltages V65 to V128 in accordance with the image signal Vd to output the bipolar segment voltage Vs. do. Each second D / A converter 313L (i.e., the second and fourth converters) selects one of the negative gradation voltages V1 to V64 in accordance with the image signal Vd to select the negative segment voltage Vs. Output Thereafter, the third and fourth D / A converters are referred to as first and second D / A converters. This is because the third and fourth D / A converters include a pair of first and second D / A converters. However, one of ordinary skill in the art may readily understand the present embodiment.
    The first time division switch 341a is connected between the output terminal of the first D / A converter 313H and the pair of first intermediate terminals Ma1 and Ma2. The first time division switch 341a connects the output terminal of the first D / A converter 313H and the first intermediate terminal Ma1 in response to the rising edge of the time division control signal J, and further, the time division control signal J In response to the falling edge of), the output terminal of the first D / A converter 313H and the first intermediate terminal Ma2 are connected.
    The second time division switch 341b is connected between the output terminal of the second D / A converter 313L and the pair of second intermediate terminals Mb1 and Mb2. The second time division switch 341b connects the output terminal of the second D / A converter 313L to the second intermediate terminal Mb1 in response to the rising edge of the time division control signal J and also the time division control signal J. In response to the falling edge of, the output terminal of the second D / A converter 313L is connected to the second intermediate terminal Mb2.
    The first polarity switching switch 352 is connected between the first intermediate terminal Ma1 and the first and second pads P1 and P2, and the second polarity switching switch 352 is connected to the first intermediate terminal Ma2 and the first polarity switching switch 352. It is connected between the third and fourth pads P3 and P4. The third polarity switching switch 352 is connected between the second intermediate terminal Mb1 and the first and second pads P1 and P2, and the fourth polarity switching switch 352 is connected to the second intermediate terminal Mb2 and the first polarity switching switch 352. It is connected between the third and fourth pads P3 and P4.
    The first polarity switching switch 352 connects the first intermediate terminal Ma1 and the first pad P1 between the odd horizontal syringes, and the second polarity switching switch 352 is connected to the first intermediate terminal Ma2. The third pad P3 is connected. The third polarity switching switch 352 connects the second intermediate terminal Mb2 and the second pad P2, and the fourth polarity switching switch 352 is the second intermediate terminal Mb2 and the fourth pad P4. Connect In this way, the positive segment voltage Vs is supplied from the first D / A converter 313H to the first and third pads P1 and P3, and the negative segment voltage Vs is supplied to the second D / A converter 313L. ) Is supplied to the second and fourth pads P2 and P4.
    During the even number of horizontal syringes, the first polarity switching switch 352 connects the first intermediate terminal Ma1 and the second pad P2, and the second polarity switching switch 352 is connected to the first intermediate terminal Ma2. The fourth pad P4 is connected. The third polarity switching switch 352 connects the second intermediate terminal Mb1 and the first pad P1, and the fourth polarity switching switch 352 has the second intermediate terminal Mb2 and the third pad P3. Connect In this way, the positive segment voltage Vs is supplied to the second and fourth pads P2 and P4 from the first D / A converter 313H, and the negative segment voltage Vs is supplied to the second D / A converter 313L. ) Is supplied to the first and third pads P1 and P3.
    The third embodiment has the following advantages.
    (1) The first and second time division switches 341a and 341b transmit the segment voltage Vs from the first and second D / A converters 313H and 313L to the first to fourth pads P1 during one horizontal syringe. To P4). Therefore, the number of the first and second D / A converters 313H and 313L is 1/4 of the number of the first to fourth pads P1 to P4. As a result, the size of the IC chip 336f is reduced, so that the number of pixels for the liquid crystal display panel can be increased.
    (2) The first and second D / A converters 313H and 313L have a simpler structure and a smaller circuit area than the D / A converter 313 in FIG.
    (3) The positive and negative segment voltages Vs from the first and second D / A converters 313H and 313L are selective to the first to fourth pads P1 to P4 by the polarity changeover switch 352. Is supplied. In this way, the screen flickering is reduced because the potential difference between the common voltage Vcom and the segment voltage Vs is stably supplied every one horizontal syringe.
    Fig. 26 is a block diagram of the IC chip 336g of the data driver for driving the color liquid crystal display panel in the modification according to the second embodiment. The IC chip 336g has three pad groups PR, PG and PB corresponding to the display color (red, green, blue). The red pads PR, the green pads PG, and the blue pads PB are sequentially arranged.
    The digital unit 360 includes three system shift registers (not shown) corresponding to three colors (red, green, blue), latch circuits 361R, 361G, 361B, three system D / A converters 313R, 313G, 313B) and a plurality of time division switches 341. 26 illustrates three system latch circuits 361R, 361G, 361B.
    The first time division switch 341 selectively switches the connection between the output terminal of the red D / A converter 313R and the two red pads PR in response to the time division control signal J. FIG. The second time division switch 341 selectively switches the connection between the output terminal of the green D / A converter 313G and the two green pads PG in response to the time division control signal J. FIG. The third time division switch 341 selectively switches the connection between the output terminal of the blue D / A converter 313B and the two blue pads PB. In this way, the segment voltage Vs is supplied to the pads PR and PG.PB selected from the D / A converters 313R, 313G and 313B during one horizontal syringe. In this way, the number of D / A converters 313R, 313G, and 313B is half the number of pads PR, PG, and PB. In addition, the internal connection wiring pattern connecting the three system latch circuits 361R, 361G, 361B and the three system D / A converters 313R, 313G, 313B is simplified.
    The modification of FIG. 26 is also applicable to the IC chip 336f according to the third embodiment. In this case, the first to fourth pad groups P1 to P4 are arranged at the positions of the pads PR, PG and PB.
    In the second and third embodiments, the number of pads connected to one time division switch may be two or more. For example, when the time division switch is connected to three pads, the time division control signal J is generated in the period divided by three horizontal syringe sections. With this configuration, the number of D / A converters is 1/3 of the number of pads.
    (Example 4)
    27 is a block diagram of a data driver 423 according to a fourth embodiment of the present invention. The data driver 423 includes a plurality of first to fourth digital-to-analog (D / A) converter groups 411 to 414, a plurality of pairs of first and second input switching circuits 425a and 415b, and a plurality of firsts. And second output switching circuits 426a and 416b, shift registers, and latch circuits (not shown). The second input switching circuit 415b and the second output switching circuit 416b have the same configuration as the input switching circuit 215b and the output switching circuit 216b of the conventional example of FIG. Fig. 27 shows only four first to fourth D / A converters 411 to 414 for four data lines DL1 to DL4.
    The first input switching circuit 425a selects one of the image signals D1n or D2n supplied from the latch circuit according to the switching signal S1 and the predetermined number of pixel selection signals S2 to remove the selected image signals. It is supplied to the 1 D / A converter 411. The first switching circuit 425a also selects the other of the image signals D1n or D2n and outputs the selected image signal to the second D / A converter 412. The number of the polarity switching signal S1 and the predetermined number of element selection signals S2 is output from the control circuit 400.
    The second input switching circuit 425b sends the image signal D3n to the third D / A converter 413 and the image signal D4n in response to the polarity switching signal S1 having the H level. Supply to A converter 414. In addition, the input switching circuit 415b transmits the image signal D3n to the fourth D / A converter 414 and the image signal D4n in response to the polarity switching signal S1 having the L level. Supply to converter 413.
    The first output switching circuit 426a is the bipolar voltage Vs1 or the second D / A converter 412 from the D / A converter 411 according to the number of the bipolar switching signal S1 and the pixel selection signal S2. One of the negative voltages Vs2 from is selected, and this selected polarity voltage is supplied to the output terminal P1. The output switching circuit 426a also supplies the other of the positive voltage Vs1 and the negative voltage Vs2 to the output terminal P2. The details of the output switching circuit 426a will be described later.
    The second output switching circuit 416b transfers the bipolar voltage Vs3 to the output terminal P3 and the fourth D / A from the third D / A converter 413 in response to the bipolar switching signal S1 having the H level. The negative voltage Vs4 is supplied from the converter 414 to the output terminal P4, respectively. The output switching circuit 416b also supplies the positive voltage Vs3 to the output terminal P4 and the negative voltage Vs4 to the output terminal P3 in response to the polarity switching signal S1 having the L level.
    28 is a block diagram of an output switching circuit 426a. The output switching circuit 426a includes four CMOS transmission gates 417a to 417d, an inverter circuit 418, and an exclusive OR (EOR) circuit 427.
    The transfer gates 417a and 417c are connected between the output terminal of the first D / A converter 411 and the output terminals P1 and P2. The transfer gates 417b and 417d are connected between the output terminal of the second D / A converter 412 and the output terminals P1 and P2.
    The inverter circuit 418 includes input terminals (i.e., node N1) and transfer gates 417a and 417d connected to the NMOS transistor gates of the transfer gates 417a and 417d and the PMOS transistor gates of the transfer gates 417b and 417c. Has an output terminal (i.e., node N2) connected to the PMOS transistor gate and the NMOS transistor gates of the transfer gates 417b and 417c.
    The EOR circuit 427 includes two CMOS transfer gates 428a and 428b and three inverter circuits 429a to 429c. The PMOS transistor gate of the transfer gate 428a and the NMOS transistor gate of the transfer gate 428b receive a certain number of pixel selection signals S2. The NMOS transistor gate of the transfer gate 428a and the PMOS transistor gate of the transfer gate 428b receive a predetermined number of pixel selection signals S2 inverted by the inverter circuit 429c.
    When the predetermined number of pixel selection signals S2 are at the L level, the transfer gate 428a is electrically connected, and the transfer gate 428b is not electrically connected. In this case, the polarity switching signal S1 is supplied to the node N1 through the transmission gate 428b and the inverter circuit 429b. Then, when the polarity switching signal S1 is at the H level, the transfer gates 417a and 417d are electrically connected, and the transfer gates 417b and 417c are not electrically connected. In this manner, the positive voltage Vs1 from the first D / A converter 411 is supplied to the output terminal P1 through the transmission gate 417a, and the negative voltage (from the second D / A converter 412 is applied. Vs2 is supplied to the output terminal P2 via the transfer gate 417d.
    In addition, when the polarity switching signal S1 is at the L level, the transfer gates 417b and 417c are electrically connected, and the transfer gates 417a and 417d are not electrically connected. In this way, the positive voltage Vs1 from the first D / A converter 411 is supplied to the output terminal P2 through the transmission gate 417c, and the negative voltage (V2) from the second D / A converter 412 is applied. Vs2 is supplied to the output terminal P1 via the transfer gate 417b.
    If the predetermined number of pixel selection signals S2 is at the H level, the transfer gate 428b is electrically connected and the transfer gate 428a is not electrically connected. In this case, the polarity switching signal S1 is supplied to the node N1 through the inverter circuit 429a, the transfer gate 428a and the inverter circuit 429b. If the polarity switching signal S1 is then at the H level, the transfer gates 417b and 417c are electrically connected, and the transfer gates 417a and 417d are not electrically connected. In this way, the positive voltage Vs1 from the first D / A converter 411 is supplied to the output terminal P2 through the transmission gate 417c, and the negative voltage (V2) from the second D / A converter 412 is applied. Vs2 is supplied to the output terminal P1 via the transfer gate 417b.
    If the polarity switching signal S1 is at the L level, the transfer gates 417a and 417d are electrically connected, and the transfer gates 417b and 417c are not electrically connected. In this manner, the positive voltage Vs1 from the first D / A converter 411 is supplied to the output terminal P1 through the transmission gate 417a, and the negative voltage (from the second D / A converter 412 is applied. Vs2 is supplied to the output terminal P2 via the transfer gate 417d.
    The polarity switching signal S1 is switched to H level or L level for each horizontal syringe. However, the polarity switching signal S1 is inverted every two or more horizontal syringes. It is preferable to set the predetermined number of pixel selection signals S2 to L level in order to invert the polarity in point units (1 pixel cell). It is preferable to set the H level in order to reverse control the polarity. In other words, when the polarity is inverted in units of two points, the luminance imbalance of the pixel cell, that is, the image flicker, is surely reduced. The level of the predetermined number of pixel selection signals S2 is set by the control circuit 400 in accordance with a setting signal from an external device.
    [1-point reversal control]
    As shown in FIG. 29, the input switching circuit 425a receives the image signals D1n and D2n in response to the polarity switching signal S1 having the H level and the predetermined number of pixel selection signals S2 having the L level. And second D / A converters 411 and 412, respectively. The input switching circuit 415b supplies the image signals D2n and D4n to the third and fourth D / A converters 411 and 412, respectively, in response to the polarity switching signal S1 having the H level.
    The output switching circuit 426a outputs the positive and negative voltages Vs1 and Vs2 in response to the polarity switching signal S1 having the H level and the predetermined number of pixel selection signals S2 having the L level. Supply to P2). The output switching circuit 416b supplies the positive and negative voltages Vs3 and Vs4 to the output terminals P3 and P4, respectively, in response to the polarity switching signal S1 having the H level.
    As shown in FIG. 30, the input switching circuit 425a receives the image signals D1n and D2n in response to the polarity switching signal S1 having the L level and the predetermined number of pixel selection signals S2 having the L level. And first D / A converters 421 and 411, respectively. The input switching circuit 415b supplies the image signals D3n and D4n to the fourth and third D / A converters 414 and 413, respectively, in response to the polarity switching signal S1 having the L level.
    The output switching circuit 426a outputs the positive and negative voltages Vs1 and Vs2 in response to the polarity switching signal S1 having the L level and the predetermined number of pixel selection signals S2 having the L level. It supplies to P1), respectively. The output switching circuit 416b supplies the positive and negative voltages Vs3 and Vs4 to the output terminals P4 and P3, respectively, in response to the polarity switching signal S1 having the L level.
    As described above, the data driver 423 generates a pair of output terminals P1, P2, or P3, P4 for each of the horizontal syringes so that voltages supplied to adjacent output terminals can have different polarities. Alternately supply. In other words, the polarity of the image signal is inverted in units of pixel cells.
    [2-point reversal control]
    As shown in FIG. 31, the input switching circuit 425a receives the image signals D1n and D2n in response to the polarity switching signal S1 having the H level and the predetermined number of pixel selection signals S2 having the L level. And first D / A converters 412 and 411, respectively. The input switching circuit 415b supplies the image signals D3n and D4n to the third and fourth D / A converters 413 and 414, respectively, in response to the polarity switching signal S1 having the H level.
    The output switching circuit 426a outputs the positive and negative voltages Vs1 and Vs2 in response to the polarity switching signal S1 having the H level and the predetermined number of pixel selection signals S2 having the H level. Supply to P2). The output switching circuit 416b supplies the positive and negative voltages Vs3 and Vs4 to the output terminals P3 and P4, respectively, in response to the polarity switching signal S1 having the H level.
    The polarity voltage is also applied to two pairs of output terminals (not shown) adjacent to the two pairs of output terminals P1 to P4 in the same manner as shown in FIG.
    As shown in FIG. 32, the input switching circuit 425a receives the image signals D1n and D2n in response to the polarity switching signal S1 having the L level and the predetermined number of pixel selection signals S2 having the H level. And second D / A converters 411 and 412, respectively. The input switching circuit 415b supplies the image signals D3n and D4n to the fourth and third D / A converters 414 and 413, respectively, in response to the polarity switching signal S1 having the L level.
    The output switching circuit 426a outputs the positive and negative voltages Vs1 and Vs2 in response to the polarity switching signal S1 having the L level and the predetermined number of pixel selection signals S2 having the H level. Supply to P2). The output switching circuit 416b supplies the positive and negative voltages Vs3 and Vs4 to the output terminals P4 and P3, respectively, in response to the polarity switching signal S1 having the L level.
    The polarity voltage is also applied to two pairs of output terminals (not shown) adjacent to the two pairs of output terminals P1 to P4 in the same manner as shown in FIG.
    As described above, the data driver 423 generates a pair of output terminals P1, P2 or P3 for each of the horizontal syringes so that the voltage supplied to two adjacent output terminals among the four output terminals is the same. Alternately supply to P4). In other words, the input and output switching circuits 425a and 426a and the input and output switching circuits 415b and 416b perform reverse switching so that the polarity of the image voltage is inverted in units of two pixel cells.
    (Example 5)
    33 is a block diagram of a data driver 423a according to the fifth embodiment of the present invention. The data driver 423a differs in the arrangement of the D / A converters 411 to 413 from the fourth embodiment. In other words, the second and third D / A converters 412 and 414 generating negative voltage are adjacent. The third D / A converter 413 generating the bipolar voltage and the D / A converter generating the bipolar voltage (not shown) are adjacent to each other. In the fifth embodiment, the logic level of the predetermined number of pixel selection signals S2 is set as in the fourth embodiment. In this way, the data driver 423a according to the fifth embodiment operates in the same manner as in the fourth embodiment.
    The fifth embodiment places the D / A converters generating the same polarity voltage adjacent to each other, thereby placing the D / A converter generating the bipolar voltage in the n-type well region and the D / A converter generating the negative voltage. It can be formed in the region of the -type substrate. When alternately arranging the D / A converters 411 and 413 for generating the positive voltage and the D / A converters 412 and 414 for generating the negative voltage, a separation region for separating the n-well region and the p-substrate region is provided. Required between transducers 411 and 414. However, adjacent arrangements do not require a separation area between the D / A converters. In this way, the area where the D / A converters 411 to 414 are formed, that is, the circuit area of the data driver 423a is reduced.
    (Example 6)
    34 is a block diagram of a data driver 423b according to the sixth embodiment of the present invention. The data driver 423b includes a pair of input and output switching circuits 430 and 431 assigned to the first to fourth D / A converters 411 to 414.
    The input switching circuit 430 selectively supplies the image signals D1n and D2n to the first and second D / A converters 411 and 412, and supplies the image signals D3n and D4n to the third and fourth D / A converters. (413, 414).
    The output switching circuit 431 selectively supplies the polarity voltages Vs1 and Vs2 from the first and second D / A converters 411 and 412 to the output terminals P1 and P2, and the third and fourth D / As. The polarity voltages Vs3 and Vs4 from the converters 413 and 414 are selectively supplied to the output terminals P3 and P4.
    The input and output switching circuits 430 and 431 have eight connection patterns A1 to A8. The input and output switching circuits 430 and 431 perform the switching operation shown in Figs. 29 to 31 by the combination of the eight connection patterns A1 to A8 in accordance with the control signals.
    Input and output switching circuits 430 and 431 may be connected to three or more D / A converters. In other words, the polarities of the voltages supplied to three or more output terminals are controlled to be the same as the polarities of the voltages supplied to three or more adjacent output terminals. Therefore, the polarity of the image voltage is inverted in units of three or more points (three pixel cells).
    35 is a block diagram of a data driver 423 according to the seventh embodiment. The data driver 423 includes buffer circuits connected between the output terminals of the first and fourth D / A converters 411 to 414 and the output switching circuits 426a and 416b, respectively.
    36 is a block diagram of a data driver 423 according to the eighth embodiment. The data driver 423 includes a buffer circuit 433 connected between the output switching circuits 426a and 416b and the output terminals P1 to P4, respectively. The buffer circuit 432 or 433 improves the driving performance of the pixel. The data driver 423 may also include buffer circuits 432 and 433.
    It will be apparent to those skilled in the art that the present invention may be practiced in many different forms without departing from the spirit and scope of the invention. Especially this invention can also be implemented with the following forms.
    37 is a block diagram of an eighth modification of the data driver 54. The data driver 54 is an N-channel MOS transistor 52 connected in series between the output terminals of the first and second D / A converters 12 and 13 (ie, node N1 and node N2). And a P-channel MOS transistor 53. The node N3 between the N-channel MOS transistor 52 and the P-channel MOS transistor 53 is connected to a wiring 44 to which a predetermined voltage Vr2 is applied. The first voltage V1 is supplied to the gate of the N-channel MOS transistor 52, and the second voltage V2 is supplied to the gate of the P-channel MOS transistor 53. The first voltage V1 is set to the minimum value of the first bipolar segment voltage Vs1, and the second voltage V2 is set to the maximum value of the second bipolar segment voltage Vs2. The predetermined voltage is set to a voltage between the first and second voltages V1 and V2. The N-channel MOS transistor 52 is turned off when the voltage of the node N1 rises to the first voltage V1, and the voltage of the node N2 is the second voltage V2 of the P-channel MOS transistor 53. Off when descending to). In this way, the first D / A converter 12 reduces the charge amount corresponding to the voltage difference between the predetermined voltage Vr1 and the common voltage Vcom, and supplies only the remaining charge amount. As a result, the time for charging to the desired bipolar segment voltage is shortened, reducing power consumption.
    When the first transistor 52 is turned off, the predetermined voltage Vr2 is set to be equal to or less than the minimum value of the first bipolar segment voltage Vs1 and when the second transistor 53 is turned off, the second negative segment voltage Vs2 is turned on. It is preferable to set above the maximum value. As a result, the data lines connected to the first and second D / A converters 12 and 13 to the output terminals P1 and P2 are reliably filled with the first and second gray voltages Va1 to Va64 and Vb1 to Vb64. Can be discharged.
    In addition, when the transistor 52 is turned off earlier than the transistor 53, a node N1 is charged through the transistor 53, the wiring 44, and any transistor 52 that remains on. In other words, the remaining charge due to the discharge of the node N2 is used to charge a certain node N1 through the wiring 44. In this way, the first D / A converter 12 starts charging from the first voltage V1. When the transistor 53 is turned off earlier than the transistor 52, the node 53 connected to the transistor 52 which maintains the on state and the transistor 52 which maintains the on state through the node N2 connected to the wiring 44 are maintained. (N1) is charged. In this way, the second D / A converter 13 starts to discharge from the second voltage V2. As a result, charging efficiency is improved.
    This invention can also be implemented with the liquid crystal display panel with a driver in which a data driver was mounted in the liquid crystal display panel. The present invention can also be implemented with a display device equipped with a plasma display panel (PDP) or an electroluminescent (EL) panel.
    Therefore, the above-described embodiments are for illustrative purposes only and may be modified and modified within the scope of the appended claims.
    According to the present invention, it is possible to provide a driver for a liquid crystal display panel which reduces the circuit area and power consumption as described above and improves the image quality of the liquid crystal display panel.
    权利要求:
    Claims (38)
    [1" claim-type="Currently amended] Each of the first and second D / A converters has an output terminal,
    Each of the first D / A converters receives an image signal and outputs a positive voltage, and each of the second D / A converters receives an image signal and outputs a negative voltage. With D / A converter,
    Each of the first polarity changeover switches is connected to the output terminals of the first and second D / A converters, and alternately outputs the positive and negative voltages in response to the polarity changeover signal, respectively. A plurality of pairs of first and second polarity switching switches connected to the output terminals of the first and second D / A converters and alternately outputting reverse polarity voltages as opposed to the first polarity switching switches in response to a polarity switching signal; Wow,
    A first node each of the switching elements located between an output terminal of the first D / A converter and the first polarity switching switch and a second node located between an output terminal of the second D / A converter and the second polarity switching switch Wherein each of the switching elements includes a plurality of switching elements that operate until the voltages of the first and second nodes are approximately equal.
    [2" claim-type="Currently amended] The display panel driver of claim 1, wherein each of the switching elements includes a MOS transistor having a gate connected to one of a first node and a second node.
    [3" claim-type="Currently amended] 3. The display panel driver according to claim 2, wherein the MOS transistor is an N-channel MOS transistor having a source and a drain connected to the first and second nodes and a gate connected to the second node.
    [4" claim-type="Currently amended] 3. The display panel driver according to claim 2, wherein the MOS transistor is a P-channel MOS transistor having a source and a drain connected to the first and second nodes and a gate connected to the first node.
    [5" claim-type="Currently amended] 2. The device of claim 1, wherein each of the switching elements comprises first and second N-channel MOS transistors connected in series between first and second nodes, and wherein a first N-channel MOS transistor gate is connected to the first and second nodes. And a gate of the second N-channel MOS transistor receives a predetermined voltage, connected to a node between the second N-channel MOS transistors.
    [6" claim-type="Currently amended] 2. The device of claim 1, wherein each of the switching elements comprises first and second N-channel MOS transistors connected in series between first and second nodes, wherein a gate of the first N-channel MOS transistor is connected to the first N-channel MOS transistor. And a node between a second N-channel MOS transistor, a gate of the second N-channel MOS transistor is connected to a second node, and a predetermined voltage is applied to the node between the first and second N-channel MOS transistors. Driver for display panel, characterized in that.
    [7" claim-type="Currently amended] 2. The switching device of claim 1, wherein each of the switching elements includes an N-channel MOS transistor and a P-channel MOS transistor connected in series between a first node and a second node, and the gate of the P-channel MOS transistor has a first predetermined voltage. And a second predetermined voltage is applied to the N-channel MOS transistor gate.
    [8" claim-type="Currently amended] 2. The switching device of claim 1, wherein each of the switching elements includes an N-channel MOS transistor and a P-channel MOS transistor connected in series between a first node and a second node, and the gate of the P-channel MOS transistor has a first predetermined voltage. And a second predetermined voltage is applied to an N-channel MOS transistor gate, and a predetermined voltage is applied to a node between the N-channel and P-channel MOS transistors.
    [9" claim-type="Currently amended] The display panel driver of claim 1, wherein each of the switching elements includes a diode having an anode connected to a second node and a cathode connected to the first node.
    [10" claim-type="Currently amended] Each of the first and second D / A converters has an output terminal, and each of the first D / A converters receives an image signal and alternately outputs a positive voltage and a negative voltage, and the second D / A A plurality of pairs of first and second D / A converters each of which receives an image signal and alternately outputs a negative voltage and a positive voltage as opposed to the first D / A converter;
    A plurality of pairs of first and second switching circuits, each of which is connected between output terminals of the first and second D / A converters,
    Each of the first and second switching circuits is electrically connected such that the voltages of the output terminals of the first and second D / A converters are substantially equal to each other based on the output voltages of the first D / A converters,
    Each of the first and second switching circuits is electrically connected such that the voltages at the output terminals of the first and second D / A converters are substantially equal to each other based on the output voltages of the second D / A converters. Driver for display panel.
    [11" claim-type="Currently amended] 11. The apparatus of claim 10, wherein the first switching circuit comprises a first MOS transistor connected between an output terminal of a first and a second D / A converter, and an output terminal of the first MOS transistor gate and the first D / A converter. A second MOS transistor connected to and receiving a polarity switching signal at a gate, and a third MOS transistor connected between the first MOS transistor gate and a low potential power supply and receiving a polarity switching signal at a gate,
    The second switching circuit is connected between a fourth MOS transistor connected between the output terminals of the first and second D / A converters, and an output terminal of the fourth MOS transistor gate and the second D / A converter, and also has a polarity at the gate. And a fifth MOS transistor receiving a switching signal and a sixth MOS transistor connected between the fourth MOS transistor gate and the low potential power supply and receiving a polarity switching signal at the gate.
    [12" claim-type="Currently amended] 11. The apparatus of claim 10, wherein the first switching circuit comprises a first MOS transistor connected between an output terminal of a first and a second D / A converter, and an output terminal of the first MOS transistor gate and the first D / A converter. A second MOS transistor connected to and receiving a polarity switching signal at the gate,
    And the second switching circuit comprises a third MOS transistor connected between the gate of the first MOS transistor and the output terminal of the second D / A converter and receiving a polarity switching signal at the gate.
    [13" claim-type="Currently amended] A liquid crystal display panel having a plurality of pairs of first and second data lines;
    A driver connected to the plurality of pairs of first and second data lines, the driver
    A plurality of pairs of outputs having the output terminal, wherein each of the first D / A converters receives an image signal and outputs a positive voltage, and each of the second D / A converters receives an image signal and outputs a negative voltage First and second D / A converters,
    Each of the first polarity switching switches is connected between the output terminals of the first and second D / A converters and the first data line, so that a positive voltage and a negative voltage are applied to the first data line in response to a polarity switching signal. Alternately output, each of the second polarity switching switches is connected between the output terminals of the first and second D / A converters and the second data line, and in reverse to the first polarity switching switch in response to the polarity switching signal; A plurality of pairs of first and second polarity switching switches for alternately outputting a polarity voltage to the second data line;
    Each of the switching elements is connected between a first node located between the output terminal of the first D / A converter and the first data line, and between a second node located between the output terminal of the second D / A converter and the second polarity switching switch. And a plurality of switching elements connected to each other and operating until the voltages of the first and second nodes become substantially equal to each other.
    [14" claim-type="Currently amended] The liquid crystal display device of claim 13, wherein each of the switching elements comprises an N-channel MOS transistor having a source and a drain connected to the first and second nodes, and a gate connected to the second node.
    [15" claim-type="Currently amended] A plurality of D / A converters for receiving an image signal and outputting a display voltage;
    A plurality of output terminal groups assigned to the plurality of D / A converters,
    A plurality of time-division switches connected respectively between the D / A converter and the output terminal group and operated by a time-division control signal to time-divisionally supply the display voltage from the D / A converter to the output terminal group. Panel driver.
    [16" claim-type="Currently amended] The display panel driver according to claim 15, wherein the number of the plurality of output terminal groups corresponds to the number of pixels during one horizontal syringe section of the display panel.
    [17" claim-type="Currently amended] 16. The apparatus of claim 15, wherein the plurality of D / A converters comprises: a first plurality of D / A converters corresponding to a first display color, a second plurality of D / A converters corresponding to a second display color, and a third A third plurality of D / A converters corresponding to the display color;
    The plurality of output terminal groups includes a first plurality of output terminal groups corresponding to the first plurality of D / A converters, a second plurality of output terminal groups corresponding to the second plurality of D / A converters, and a third plurality of output terminal groups. And a third plurality of output terminal groups corresponding to the D / A converters of the display panel.
    [18" claim-type="Currently amended] The display panel driver of claim 15, further comprising a time division signal generation circuit configured to generate a time division control signal in response to the latch control pulse signal.
    [19" claim-type="Currently amended] 19. The apparatus of claim 18, wherein the time division signal generation circuit comprises: a time division setting circuit for receiving a latch control pulse signal and generating a timing signal;
    And a control circuit which receives the timing signal and generates a time division control signal.
    [20" claim-type="Currently amended] 20. The display panel driver according to claim 19, wherein the time division control signal has a predetermined pulse width obtained by dividing one horizontal syringe interval by the number of output terminals of one group.
    [21" claim-type="Currently amended] A system for supplying timing signals to a plurality of display panel drivers including first and second drivers each having a semiconductor integrated circuit,
    A wiring for connecting the first and second drivers in series,
    The first driver
    A plurality of D / A converters for receiving an image signal and outputting a display voltage;
    A plurality of output terminal groups assigned to the plurality of D / A converters,
    A plurality of time division switches each connected between each of the D / A converters and respective groups of the output terminals, for time-divisionally supplying display voltages from the D / A converters to the respective groups of output terminals according to a time division control circuit;
    A time division setting circuit for generating a timing signal in response to a latch control pulse signal to supply the timing signal to the wiring;
    A control circuit for receiving the timing signal and generating a time division control signal,
    The second driver
    A plurality of D / A converters for receiving an image signal and outputting a display voltage;
    A plurality of output terminal groups assigned to the plurality of D / A converters,
    A plurality of time-division switches connected between each of the D / A converters and respective groups of the output terminals, respectively, for time-divisionally supplying display voltages to the respective output terminals of each group from the D / A converters according to time-division control circuits;
    And a control circuit which receives a timing signal from the first driver through the wiring and generates a time division control signal.
    [22" claim-type="Currently amended] 22. The timing signal supply system according to claim 21, wherein each of the time division setting circuits includes a transmission gate which is maintained in a conductive state and transmits a latch control pulse signal to the wiring and the control circuit.
    [23" claim-type="Currently amended] 22. The apparatus of claim 21, wherein the time division setting circuit of the first driver includes a transmission gate that is always in a conductive state and transmits a latch control pulse signal to the wiring and the control circuit.
    The time division setting circuit of the second driver includes a transmission gate that is always maintained in a conductive state, and is configured to supply a timing signal supplied from the first driver to the second driver control circuit through the wiring. Timing signal supply system of the driver.
    [24" claim-type="Currently amended] 22. The timing signal supply system according to claim 21, wherein the time division control signal has a predetermined pulse width obtained by dividing one horizontal syringe interval by the number of output terminals in one group.
    [25" claim-type="Currently amended] 25. The system as claimed in claim 24, wherein the first driver is arranged such that the timing of the latch control pulse signal for the time division setting circuit is substantially coincident with the time point at which the time division control signal pulse switches.
    [26" claim-type="Currently amended] A first plurality of D / A converters for receiving an image signal and outputting a bipolar display voltage;
    A second plurality of D / A converters for receiving an image signal and outputting a negative display voltage;
    A first plurality of pairs of intermediate terminals assigned to the first plurality of D / A converters,
    A second plurality of pairs of intermediate terminals assigned to the second plurality of D / A converters,
    Connected between each of the first plurality of D / A converters and each of the first plurality of pairs of intermediate terminals, and time-dividing the bipolar display voltage from each of the first plurality of pairs of intermediate terminals from the D / A converter according to a time division control signal. A first plurality of time division switches to be supplied to the
    Connected between each of the second plurality of D / A converters and each of the second plurality of pairs of intermediate terminals, and time-dividing the negative display voltage from each of the second plurality of pairs of intermediate terminals from the D / A converter according to the time division control signal. A plurality of second time division switches to be supplied to the
    A plurality of pairs of output terminals including first and second output terminals assigned to the first and second plurality of pairs of intermediate terminals;
    A first plurality of pairs of polarity switching switches for selectively connecting a pair of the first plurality of pairs of intermediate terminals and first and second pairs of the plurality of pairs of output terminals, respectively, in accordance with a polarity switching signal;
    And a second plurality of polarity switching switch pairs for selectively connecting one of the second plurality of pairs of intermediate terminals and the first and second pairs of the plurality of pairs of output terminals according to the polarity switching signal, respectively. Driver for display panel.
    [27" claim-type="Currently amended] A liquid crystal display panel having a plurality of data line groups.
    A driver for driving the liquid crystal display panel;
    The driver
    A plurality of D / A converters for receiving an image signal and outputting a display voltage;
    A plurality of output terminal groups assigned to the plurality of D / A converters and connected to the plurality of data line groups;
    A plurality of time-division switches connected between each D / A converter and output terminals of each group, and time-divisionally supplying display voltages from the D / A converter to the output terminals of each group according to time-division control signals. Liquid crystal display.
    [28" claim-type="Currently amended] Each first D / A converter receives an image signal and outputs a bipolar voltage, and each second D / A converter receives an image signal and outputs a negative voltage and a plurality of pairs of first and second D / A converters Wow,
    Each switching circuit is connected to each pair of first and second D / A converters, and a plurality of pairs of first and second input switching circuits for selectively supplying image signals to the first and second D / A converters, respectively; ,
    A plurality of pairs of first and second output terminals corresponding to the plurality of pairs of first and second D / A converters,
    Each switching circuit is connected between each pair of first and second D / A converters and each pair of first and second output terminals, and has a bipolar voltage from the first and second D / A converters to the first and second output terminals. A plurality of pairs of first and second output switching circuits for selectively supplying a negative voltage;
    Each of the first input and first output switching circuits, wherein a voltage having a different polarity is supplied to an adjacent output terminal of an adjacent pair of output terminals in a first mode, and a voltage having the same polarity in a second mode And a plurality of control circuits for controlling the plurality of first input and output switching circuits to be supplied to adjacent pairs of output terminals.
    [29" claim-type="Currently amended] 29. The driver as claimed in claim 28, wherein each control circuit controls each of the first input and first output switching circuits in units of one or more horizontal syringes in a second mode.
    [30" claim-type="Currently amended] 29. The driver as claimed in claim 28, wherein the first and second D / A converters are alternately arranged.
    [31" claim-type="Currently amended] 31. The method of claim 30, wherein each control circuit performs the same switching operation in response to the first switching signal in which the first input and the first output switching circuit and the second input and the second output switching circuit indicate the first mode, Control each first input and first output switching circuit such that the first input and first output switching circuit and the second input and second output switching circuit perform an inverted switching operation in response to a second switching signal indicative of the second mode. A display panel driver, characterized in that.
    [32" claim-type="Currently amended] 29. The driver as claimed in claim 28, wherein the two first and second D / A converters are alternately arranged.
    [33" claim-type="Currently amended] 33. The apparatus of claim 32, wherein each control circuit performs an inverted switching operation in response to a first switching signal in which the first input and the first output switching circuit and the second input and the second output switching circuit indicate the first mode, Control each first input and first output switching circuit such that the first input and first output switching circuit and the second input and second output switching circuit perform the same switching operation in response to a second switching signal indicative of the second mode. A display panel driver, characterized in that.
    [34" claim-type="Currently amended] The method of claim 28,
    A first plurality of pairs of buffers each pair connected between each pair of first and second D / A converters and each pair of first output switching circuits,
    And a second plurality of pairs of buffers in which each pair is connected between each pair of the first and second D / A converters and each pair of the second output switching circuits.
    [35" claim-type="Currently amended] 29. The system of claim 28, further comprising: a first plurality of pairs of buffers, each pair connected between each pair of first output switching circuits and each pair of first and second output terminals,
    And a second plurality of pairs of buffers in which each pair is connected between each pair of second output switching circuits and each pair of first and second output terminals.
    [36" claim-type="Currently amended] A liquid crystal display panel having a plurality of pairs of first and second data lines;
    A driver for driving the liquid crystal display panel,
    The driver
    A plurality of pairs of first and second D / A converters in which each first D / A converter receives an image signal and outputs a positive voltage, and each second D / A converter receives an image signal and outputs a negative voltage. Wow,
    A plurality of pairs of first and second input switching circuits connected to each pair of first and second D / A converters and selectively supplying image signals to the first and second D / A converters;
    A plurality of pairs of first and second output terminals connected to the plurality of pairs of first and second data lines and corresponding to the plurality of pairs of first and second D / A converters;
    Each output switching circuit is connected between each pair of first and second D / A converters and each pair of first and second output terminals and from the first and second D / A converters to the first and second output terminals. A plurality of pairs of first and second output switching circuits for selectively supplying a positive voltage and a negative voltage;
    A voltage pair having a different polarity in a first mode is supplied to an adjacent output terminal of an adjacent pair of output terminals in a first mode, and a voltage having the same polarity in a second mode is an adjacent pair And a plurality of control circuits for controlling the plurality of first input and first output switching circuits so as to be supplied to adjacent output terminals of the output jar of the plurality of first output switching circuits.
    [37" claim-type="Currently amended] A plurality of pairs of first and second D / A converters in which each first D / A converter receives an image signal and outputs a positive voltage, and each second D / A converter receives an image signal and outputs a negative voltage. Providing a,
    Each switching circuit is connected to each pair of respective first and second D / A converters, and a plurality of pairs of first and second input switching circuits for selectively supplying image signals to the first and second D / A converters. Providing a,
    Providing a plurality of pairs of first and second output terminals corresponding to the plurality of pairs of first and second D / A converters;
    Each switching circuit is connected between each pair of first and second D / A converters and each pair of respective first and second output terminals, respectively, the first and second outputs from the first and second D / A converters. Providing a plurality of pairs of first and second output switching circuits for selectively supplying a positive voltage and a negative voltage to a terminal;
    Controlling each first input and output switching circuit such that voltages having different polarities are supplied to adjacent output terminals of adjacent pairs of output terminals in the first mode;
    And controlling each of the first input and output switching circuits such that a voltage having the same polarity is supplied to adjacent output terminals of the adjacent pair of output terminals in the second mode.
    [38" claim-type="Currently amended] 38. The method of claim 37, wherein each of the first input and output switching circuits is controlled in units of one or more horizontal syringes in a second mode.
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    同族专利:
    公开号 | 公开日
    US6304241B1|2001-10-16|
    TW416239B|2000-12-21|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-06-03|Priority to JP15481098
    1998-06-03|Priority to JP154810
    1998-06-30|Priority to JP184175
    1998-06-30|Priority to JP18417598A
    1998-07-10|Priority to JP196233
    1998-07-10|Priority to JP10196233A
    1998-11-17|Priority to JP326419
    1998-11-17|Priority to JP32641998A
    1998-12-31|Application filed by 아끼구사 나오유끼, 후지쯔 가부시끼가이샤
    2000-01-25|Publication of KR20000004893A
    2002-06-26|Application granted
    2002-06-26|Publication of KR100327178B1
    优先权:
    申请号 | 申请日 | 专利标题
    JP15481098|1998-06-03|
    JP154810|1998-06-03|
    JP184175|1998-06-30|
    JP18417598A|JP4984337B2|1998-06-30|1998-06-30|Display panel drive circuit and display device|
    JP196233|1998-07-10|
    JP10196233A|JP2000029438A|1998-07-10|1998-07-10|Method and circuit to drive display panel, and display device|
    JP326419|1998-11-17|
    JP32641998A|JP4456190B2|1998-06-03|1998-11-17|Liquid crystal panel drive circuit and liquid crystal display device|
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